To increase memory capacity, EEPROMs having NAND structured memory cells (hereinafter, referred to as "NAND cell strings") have been developed. Referring to FIG. 1, there are shown two NAND cell strings 102 and 104 connected to bit lines BL1 and BL2, respectively. As shown, a NAND cell string 102 or 104 includes two select transistors Mss and Mgs, and memory cell transistors M1 to Mi whose drain-source paths are connected in series between a source of string select transistor Mss and a drain of ground (or source) select transistor Mgs.
Each of the memory cell transistors M1 through Mi has its drain and source spaced apart by its channel. Further, its floating gate is formed on a tunnel oxide film over the channel and its control gate is formed on an intermediate dielectric film over the floating gate. A drain of the string select transistor Mss is connected to the bit line BL1 or BL2 and a source of the ground select transistor Mgs is connected to a common source line (not shown) which is grounded during either programming or read operation. Gates of string select transistor Mss and ground select transistor Mgs are coupled with a string selection line SSL and a ground selection line GSL, respectively. Gates of memory cell transistors M1 through Mi are connected to word lines WL1 through WLi, respectively.
With the NAND structure described above, since the number of contact holes connected to the bit line per memory cell transistor is reduced, EEPROMs having a high density memory capacity can be accomplished.
A conventional program operation of NAND structured EEPROMs will be described below.
Before programming the memory transistors of a NAND structured EEPROM, an erase operation is normally performed. In this operation, the erasure of memory cell transistors M1 through Mi will be accomplished by applying an erase potential, such as 20 volts, to a semiconductor substrate and applying a reference potential, such as 0 volts (i.e., ground voltage V.sub.SS), to word lines WL1 to WLi. Electrons stored by the floating gates of memory cell transistors M1 to Mi will be extracted by Fowler-Nordheim tunneling (F-N tunneling), and thereby the memory cell transistors M1 to Mi will be changed into depletion mode transistors. It is commonly assumed that erased memory cell transistors store logic "0" data.
After such an erase operation, a program or write operation is performed as illustrated in FIG. 2 which is a timing diagram of a conventional program operation. For example, assume that memory cell transistor M5 is to be programmed. In this operation, with reference to FIG. 2, first, a power supply voltage V.sub.CC and a ground voltage V.sub.SS is applied to the string selection line SSL and ground selection line GSL, respectively. Further, each of the bit lines BL1 and BL2 is supplied with either the ground voltage V.sub.SS (data "0") or the power supply voltage V.sub.CC (data "1") in accordance with the data state to be programmed. It is assumed herein that the bit lines BL1 and BL2 are supplied with power supply voltage V.sub.CC (data "1") and the ground voltage V.sub.SS (data "0"), respectively. Subsequently, a pass voltage V.sub.pass, such as 8 volts, is applied to the word lines WL1-WL4 and WL6-WLi, i.e., unselected word lines except a selected word line WL5, and the semiconductor substrate is supplied with a reference potential, such as ground voltage V.sub.SS. After an elapse of a given time, the word lines WL4 and WL6, adjacent to the selected word line WL5, are applied with a voltage lower than the pass voltage V.sub.pass, for example, ground voltage V.sub.SS. Thereafter, a program voltage V.sub.pgm, such as 18 volts, is applied to the selected word line WL5.
In such a program operation, the string select transistor Mss in the string 102 coupled with bit line BLl of the power supply voltage V.sub.CC will be turned off so that the cell string 102 will be floated. Thus, the source, drain and channel potentials of the selected cell transistor M5 in the string 102 will be boosted up due to the capacitive coupling when the program voltage V.sub.pgm is applied to the control gate of the transistor M5 in the string 102. Namely, the difference between the control gate potential and the source-drain-chanel potential will not be large enough to permit F-N tunneling to occur. So, the selected cell transistor M5 in the string 102 will remain erased.
On the contrary, the source, drain and channel potentials of the selected cell transistor M5 in the string 104 will equal the ground voltage V.sub.SS since the string select transistor Mss in the string 104 coupled to bit line BL2 of the ground voltage V.sub.SS will be turned on, thereby electrons will be trapped and accumulate to the floating gate of the transistor M5 in the string 104 by F-N tunneling when the program voltage V.sub.pgm is applied to the control gate of the transistor M5 in the string 104. The accumulation of a large quantity of trapped electrons on the floating gate causes the effective threshold voltage of the cell transistor M5 in the string 104 to increase (e.g., about 6-7 V). Consequently, the selected cell transistor M5 in the string 104 will be changed into an enhancement mode transistor, that is, the transistor M5 of the string 104 will be programmed. It is assumed in general that a programmed memory cell transistor stores logic "1" data.
In the above-described programming, it is necessary that the unselected cell transistor adjacent to a selected cell transistor and placed between the selected cell transistor and the string select transistor Mss should remain erased in order to induce F-N tunneling. For this reason, the programing should always be performed sequentially, from the cell transistor M1 adjacent to the ground select transistor Mgs toward the cell transistor Mi adjacent to the sting select transistor Mss.